This invention relates to integrated circuit design and, more particularly, to verifiable automatic register pipelining of integrated circuit design descriptions at the register transfer level (RTL).
Every transition from one technology node to the next technology node has resulted in smaller transistor geometries and thus potentially more functionality implemented per unit of integrated circuit area. Synchronous integrated circuits have further benefited from this development as evidenced by reduced interconnect and cell delays, which has led to performance increases. However, more recent technology nodes have seen a significant slow-down in the reduction of delays and thus a slow-down in the performance increase.
Solutions such as register pipelining have been proposed to further increase the performance. During register pipelining, additional registers are inserted between synchronous elements, which lead to an increase in latency at the benefit of increased clock frequencies and throughput. However, performing register pipelining often involves spending significant time and effort because several iterations of locating performance bottlenecks, inserting or removing registers, and compiling the modified integrated circuit design are usually required.
Situations frequently arise where a register pipelined integrated circuit design still exhibits an unsatisfactory performance after many iterations of inserting or removing registers because adding a pipeline register to a given path in a current iteration may obsolete the effects of having added a register to a different path during a prior iteration.
The difficulty of performing register pipelining is further exacerbated by the facts that the latency in different paths or blocks may be related, that certain conditions such as reset removal may be latency dependent, and that verification related activities such as simulation may need to consider modifications to a test bench and a design-under-test (DUT) caused by register pipelining.